Archive for the ‘Electrical’ Category
From the New York Times, Tesla predicting cell phones:
A breakdown of the mask creation process. Original resolution available upon request (9000×6000).
Click for full resolution.
A tentative poster going over the basics of my process. More in-depth posters will be made viewable in the next couple of weeks.
Click for full resolution.
RoastedToast logo on silicon wafer. Taken via microscope viewfinder. Size is about 4mm in diameter. Each ’spec’ or ’spot’ on the toast is 25-50µm in diameter.
RoastedToast logo on silicon wafer.
A quick post today:
After working out some snags with new chemicals, this past week has finally afforded me some actual progress on my wafer lithography. I’ll explain later as I document the multi-month process, but for now here’s a trio of screencaps from the microscope. As usual, click on the images for full size.
Small Vernier scale used to gauge how the development of a particular layer is going.
Small text describing a 7mm x 2mm inductor.
Text labeling a PMOSFET.