Posts Tagged ‘cmos’
A breakdown of the mask creation process. Original resolution available upon request (9000×6000).
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A tentative poster going over the basics of my process. More in-depth posters will be made viewable in the next couple of weeks.
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RoastedToast logo on silicon wafer. Taken via microscope viewfinder. Size is about 4mm in diameter. Each ’spec’ or ’spot’ on the toast is 25-50µm in diameter.
RoastedToast logo on silicon wafer.
A quick post today:
After working out some snags with new chemicals, this past week has finally afforded me some actual progress on my wafer lithography. I’ll explain later as I document the multi-month process, but for now here’s a trio of screencaps from the microscope. As usual, click on the images for full size.
Small Vernier scale used to gauge how the development of a particular layer is going.
Small text describing a 7mm x 2mm inductor.
Text labeling a PMOSFET.
Continuing yesterday’s posting, here is another part from the senior project folder. This time a CMOS inverter (NOT gate). Positive and negative power is applied to the device, which will inverse a given input at the output. This inverter was designed at 300µm for the sake of practicality. A later post will show another CMOS inverter re-designed at 50µm. This inverter is comprised of eight process layers and masks.
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