Posts Tagged ‘µElectronics’
A breakdown of the mask creation process. Original resolution available upon request (9000×6000).
Click for full resolution.
A tentative poster going over the basics of my process. More in-depth posters will be made viewable in the next couple of weeks.
Click for full resolution.
A quick post today:
After working out some snags with new chemicals, this past week has finally afforded me some actual progress on my wafer lithography. I’ll explain later as I document the multi-month process, but for now here’s a trio of screencaps from the microscope. As usual, click on the images for full size.
Small Vernier scale used to gauge how the development of a particular layer is going.
Small text describing a 7mm x 2mm inductor.
Text labeling a PMOSFET.
Just wanted to share some pictures I snapped today of the three furnaces in action (all at once!) at different temperatures. This was the first time that all three were active at the same time (drawing ~90-100Amps). Look closely and you can see the wafers inside the furnaces.
N Type Diffusion Furnace @ 825°C
P Type Diffusion Furnace @ 925°C
Silicon Dioxide Growth Furnace @ 1075°C
Continuing yesterday’s posting, here is another part from the senior project folder. This time a CMOS inverter (NOT gate). Positive and negative power is applied to the device, which will inverse a given input at the output. This inverter was designed at 300µm for the sake of practicality. A later post will show another CMOS inverter re-designed at 50µm. This inverter is comprised of eight process layers and masks.
Click image for full resolution.
